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LTC2203/LTC2202 16-Bit, 25Msps/10Msps ADCs U
LTC2203: 128K Point FFT, fIN = 5.1MHz, -1dBFS, PGA = 0
3.3V SENSE VCM 2.2F AIN + ANALOG INPUT AIN - 1.25V COMMON MODE BIAS VOLTAGE INTERNAL ADC REFERENCE GENERATOR OVDD 0.5V TO 3.6V
FEATURES

DESCRIPTIO
Sample Rate: 25Msps/10Msps 81.6dB SNR and 100dB SFDR (2.5V Range) SFDR 90dB at 70MHz (1.667VP-P Input Range) PGA Front End (2.5VP-P or 1.667VP-P Input Range) 380MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer Single 3.3V Supply Power Dissipation: 220mW/140mW Clock Duty Cycle Stabilizer Out-of-Range Indicator Pin Compatible Family 25Msps: LTC2203 (16-Bit) 10Msps: LTC2202 (16-Bit) 48-Pin (7mm x 7mm) QFN Package
The LTC(R)2203/LTC2202 are 25Msps/10Msps, sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 380MHz. The input range of the ADC can be optimized with the PGA front end. The LTC2203/LTC2202 are perfect for demanding applications, with AC performance that includes 81.6dB SNR and 100dB spurious free dynamic range (SFDR). Maximum DC specs include 4LSB INL, 1LSB DNL (no missing codes). A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 4843302 and 6949965B1
APPLICATIO S

Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE
TYPICAL APPLICATIO
+
S/H AMP
-
16-BIT PIPELINED ADC CORE
CORRECTION LOGIC AND SHIFT REGISTER
OUTPUT DRIVERS
OF CLKOUT+ CLKOUT- D15 * * * D0 OGND CMOS OUTPUTS
CLOCK/DUTY CYCLE CONTROL
VDD GND 1F 1F
3.3V 1F
AMPLITUDE (dBFS)
CLK
PGA
SHDN
ADC CONTROL INPUTS
U
U
1F
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 GO7
DITH
MODE
OE
RAND
22032 TA01
22032fb
1
LTC2203/LTC2202 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
TOP VIEW 48 GND 47 PGA 46 RAND 45 MODE 44 OE 43 OF 42 D15 41 D14 40 D13 39 D12 38 OGND 37 OVDD
OVDD = VDD (Notes 1 and 2)
Supply Voltage (VDD) ................................... -0.3V to 4V Digital Output Supply Voltage (OVDD) .......... -0.3V to 4V Digital Output Ground Voltage (OGND)........ -0.3V to 1V Analog Input Voltage (Note 3) ..... -0.3V to (VDD + 0.3V) Digital Input Voltage .................... -0.3V to (VDD + 0.3V) Digital Output Voltage ................-0.3V to (OVDD + 0.3V) Power Dissipation............................................ 2000mW Operating Temperature Range LTC2203C/LTC2202C ............................... 0C to 70C LTC2203I/LTC2202I .............................-40C to 85C Storage Temperature Range ..................-65C to 125C
SENSE 1 VCM 2 VDD 3 VDD 4 GND 5 AIN+ 6 AIN- 7 GND 8 GND 9 CLK 10 GND 11 VDD 12
49
36 OVDD 35 D11 34 D10 33 D9 32 D8 31 OGND 30 CLKOUT+ 29 CLKOUT- 28 D7 27 D6 26 D5 25 OVDD
UK PACKAGE 48-LEAD (7mm x 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49) MUST BE SOLDERED TO PCB BOARD TJMAX = 125C, JA = 29C/W TJMAX = 150C, OPTION AVAILABLE, CONSULT FACTORY
ORDER PART NUMBER LTC2203CUK LTC2202CUK LTC2203IUK LTC2202IUK
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No missing codes) Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS Differential Analog Input (Note 5) TA = 25C Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference (2.5V Range, PGA = 0) MIN 16

VDD 13 VDD 14 GND 15 SHDN 16 DITH 17 D0 18 D1 19 D2 20 D3 21 D4 22 OGND 23 OVDD 24
UK PART* MARKING LTC2203UK LTC2202UK LTC2203UK LTC2202UK
TYP 1.2 1.5 0.3 2 10 0.2 30 15 1.92
MAX 4.0 4.5 1 10 1.5
UNITS LSB LSB LSB mV V/C %FS
ppm/C ppm/C
LSBRMS
22032fb
2
U
W
U
U
WW
W
U
LTC2203/LTC2202 A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25C. (Note 4)
SYMBOL VIN VIN, CM IIN ISENSE IMODE IOE CIN tAP tJITTER CMRR BW-3dB PARAMETER Analog Input Range (AIN+ - AIN-) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND OE Pin Pull-Down Current to GND Analog Input Capacitance Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth CONDITIONS 3.135V VDD 3.465V Differential Input (Note 7) 0V AIN+, AIN- VDD (Note 9) 0V SENSE VDD (Note 10) MIN

DY A IC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA =1 ) 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA = 1) 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA = 1) LTC2203 TYP MAX 81.6 79.4 80.0 81.6 79.4 81.4 79.3 80.8 77.5 78.9 78.3 77.2 100 100 85 100 90 100 100 95 100 90 85 95 85 90 100 100 90 100 100 100 100 100 90 100 90 90 MIN LTC2202 TYP MAX 81.6 79.4 80.0 81.6 79.4 81.4 79.3 80.8 77.5 78.9 78.3 77.2 100 100 85 100 90 100 100 95 100 90 85 95 85 90 100 100 90 100 100 100 100 100 90 100 90 90 MIN UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
22032fb
SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
SFDR
Spurious Free Dynamic Range 4th Harmonic or Higher
U
WU
U
1 -1 -3
Sample Mode CLK = 0 Hold Mode CLK = 0
TYP MAX 1.667 or 2.5 1.25 1.5 1 3 10 10 10.5 1.4 0.9 200
UNITS VP-P V A A A A pF pF ns fs RMS dB MHz
1V < (AIN+ = AIN-) <1.5V Rs < 20
80 380

3
LTC2203/LTC2202 DY A IC ACCURACY
SYMBOL S/(N+D) PARAMETER Signal-to-Noise Plus Distortion Ratio
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS unless otherwise noted. (Note 4)
CONDITIONS 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA = 1) 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA = 1) 1MHz Input (2.5V Range, PGA = 0) 1MHz Input (1.667V Range, PGA = 1) 5MHz Input (2.5V Range, PGA = 0) 5MHz Input (1.667V Range, PGA = 1) 12.5MHz Input (2.5V Range, PGA = 0) 12.5MHz Input (1.667V Range, PGA = 1) 30MHz Input (2.5V Range, PGA = 0) 30MHz Input (1.667V Range, PGA = 1) 70MHz Input (2.5V Range, PGA = 0) 70MHz Input (1.667V Range, PGA = 1) LTC2203 MIN TYP MAX 81.5 79.3
SFDR
SFDR
CO operating temperature range, otherwise specifications are at T = 25C. (Note 4) denotes the specifications which apply over O ODE BIAS CHARACTERISTICS The the full
A
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance
4
U U UU U UU
WU
LTC2202 MIN TYP MAX 81.5 79.3 79.7 81.5 79.3 81.3 79.2 80.6 78.6 78.1 77 105 105 105 105 105 105 105 105 100 100 115 115 115 115 115 115 115 115 110 110
UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
79.7
77.2
Spurious Free Dynamic Range at -25dBFS Dither "OFF"
Spurious Free Dynamic Range at -25dBFS Dither "ON"
81.5 79.3 81.3 79.2 80.6 78.6 78.1 77 105 105 105 105 105 105 105 105 100 100 115 115 115 115 115 115 115 115 110 110
77.2
100
100
CONDITIONS IOUT = 0 IOUT = 0 3.135V VDD 3.465V 1mA | IOUT | 1mA
MIN 1.15
TYP 1.25 40 1 2
MAX 1.35
UNITS V
ppm/C
mV/ V
22032fb
LTC2203/LTC2202 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER LOGIC INPUTS (CLK, OE, DITH, PGA, SHDN, RAND) VIH High Level Input Voltage VIL Low Level Input Voltage IIN Digital Input Current CIN Digital Input Capacitance LOGIC OUTPUTS OVDD = 3.3V VOH High Level Output Voltage VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL Low Level Output Voltage Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage CONDITIONS VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7)

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN 2 0.8 10 1.5 TYP MAX UNITS V V A pF
POWER REQUIRE E TS
SYMBOL VDD PSHDN OVDD IVDD PDIS PARAMETER Analog Supply Voltage Shutdown Power Output Supply Voltage Analog Supply Current Power Dissipation
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS
UW
U
U
VDD = 3.3V VDD = 3.3V VOUT = 0V VOUT = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V
IO = -10A IO = -200A IO = 160A IO = 1.6mA
3.1
3.299 3.29 0.01 0.10 -50 50
0.4
V V V V mA mA V V V V
IO = -200A IO = 1.60mA IO = -200A IO = 1.60mA
2.49 0.1 1.79 0.1
MIN 3.135 0.5
LTC2203 TYP 3.3 2 66 220
MAX 3.465 3.6 80 264
MIN 3.135 0.5
LTC2202 TYP 3.3 2 42 140
MAX 3.465 3.6 50 165
UNITS V mW V mA mW
SHDN = VDD, CLK = VDD

22032fb
5
LTC2203/LTC2202
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL fS tL tH tAP tD tC tSKEW PARAMETER Sampling Frequency CLK Low Time CLK High Time Sample-and-Hold Aperture Delay CLK to DATA Delay CLK to CLKOUT Delay DATA to CLKOUT Skew DATA Access Time Bus Relinquish Time CL = 5pF (Note 7) CL = 5pF (Note 7) CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7)

TI I G CHARACTERISTICS
CONDITIONS
Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 25MHz (LTC2203), 10MHz (LTC2202), input range = 2.5VP-P with differential drive (PGA = 0), unless otherwise specified.
TI I G DIAGRA
ANALOG INPUT
CLK
D0-D15, OF tC CLKOUT+ CLKOUT-
6
W
UW UW
MIN

LTC2203 TYP MAX 20 20 20 20 0.9 3.1 3.1 0 5 5 7 25 500 500 500 500
MIN 1 40 5 40 5
LTC2202 TYP MAX 50 50 50 50 0.9 3.1 3.1 0 5 5 7 10 500 500 500 500
UNITS MHz ns ns ns ns ns ns ns ns ns ns Cycles
Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
1 18.9 5 18.9 5
1.3 1.3 -0.6
4.9 4.9 0.6 15 15
1.3 1.3 -0.6
4.9 4.9 0.6 15 15
Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: Dynamic current from switched capacitor inputs is large compared to DC leakage current, and will vary with sample rate. Note 10: Leakage current will experience transient at power up. Keep resistance < 1K .
tAP
N+1 N+3
N+4 N+2
N tL tH
tD N-7 N-6 N-5 N-4 N-3
22032 TD01
22032fb
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: Integral Nonlinearity (INL) vs Output Code
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 CODE
22032 G01
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
COUNT
49152
LTC2203: 128K Point FFT, fIN = 1MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 GO4
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
2
8 4 6 FREQUENCY(MHz)
AMPLITUDE (dBFS)
LTC2203: 128K Point FFT, fIN = 5.1MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 GO7
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
2
8 4 6 FREQUENCY(MHz)
AMPLITUDE (dBFS)
UW
LTC2203: Differential Nonlinearity (DNL) vs Output Code
1.0 0.8 0.6 0.4 0.2 30000 20000 10000 50000 40000 60000
LTC2203: AC Grounded Input Histogram (256k Samples)
65536
0
16384
32768 CODE
49152
65536
22032 G02
0 32812 32816
32820 32824 OUTPUT CODE
32828
32832
22032 G03
LTC2203: 128K Point FFT, fIN = 1MHz, -10dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 10 12
22032 GO5
LTC2203: 128K Point FFT, fIN = 1MHz, -20dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 GO6
LTC2203: 128K Point FFT, fIN = 5.1MHz, -10dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 10 12
22032 GO8
LTC2203: 128K Point FFT, fIN = 5.1MHz, -20dBFS, PGA = 0, Internal Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 GO9
22032fb
7
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: 128K Point FFT, fIN = 5.1MHz, -20dBFS, PGA = 0, Internal Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2203: SFDR vs Input Level, fIN = 5MHz, PGA = 0, Dither "Off"
140 120 SFDR (dBc AND dBFS) 100 80 60 40 20 0 -70 SFDR (dBc AND dBFS) 140 120
80 60 40 20 0 -70
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
AMPLITUDE (dBFS)
INPUT LEVEL (dBFS)
22032 G13
LTC2203: 32K Point FFT, fIN = 12.4MHz, -10dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G16
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
8
UW
LTC2203: 32K Point 2-Tone FFT, fIN = 4.9MHz and 30.1MHz, -7dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G11
LTC2203: 32K Point 2-Tone FFT, fIN = 4.9MHz and 30.1MHz, -15dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G12
LTC2203: SFDR vs Input Level, fIN = 5MHz, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2203: 32K Point FFT, fIN = 12.4MHz, -1dBFS, PGA = 0
100
0
2
INPUT LEVEL (dBFS)
22032 G14
8 4 6 FREQUENCY(MHz)
10
12
22032 G15
LTC2203: 32K Point FFT, fIN = 12.4MHz, -20dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G17
LTC2203: SFDR vs Input Level, fIN = 12.7MHz, PGA = 0, Dither "Off"
140 120 100 80 60 40 20 0 -70
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
22032 G18
22032fb
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: SFDR vs Input Level, fIN = 12.7MHz, PGA = 0, Dither "On"
140 120 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 100 80 60 40 20 0 -70 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G20
AMPLITUDE (dBFS)
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
LTC2203: 32K Point FFT, fIN = 30MHz, -20dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G22
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
100 80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
SFDR (dBc AND dBFS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2203: 32K Point FFT, fIN = 70.1MHz, -1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
2
8 4 6 FREQUENCY(MHz)
10
12
22032 G25
0
2
8 4 6 FREQUENCY(MHz)
AMPLITUDE (dBFS)
UW
-10
LTC2203: 32K Point FFT, fIN = 30MHz, -1dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2203: 32K Point FFT, fIN = 30MHz, -10dBFS, PGA = 1
0
0
2
8 4 6 FREQUENCY(MHz)
10
12
22032 G21
22032 G19
LTC2203: SFDR vs Input Level, fIN = 30.1MHz, PGA = 0, Dither "Off"
140 120 140 120 100 80 60 40 20
LTC2203: SFDR vs Input Level, fIN = 30.1MHz, PGA = 0, Dither "On"
0
0 -70
-60
-50
-40
-30
-20
-10
0
INPUT LEVEL (dBFS)
22032 G24
22032 G23
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2203: 32K Point FFT, fIN = 70.1MHz, -10dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2203: 32K Point FFT, fIN = 70.1MHz, -20dBFS, PGA = 1
10
12
22032 G26
0
2
8 4 6 FREQUENCY(MHz)
10
12
22032 G27
22032fb
9
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: 32K Point 2-Tone FFT, fIN = 44.9MHz and 70.1MHz, -7dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G28
SFDR (dbc AND dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2203: SFDR vs Input Level, fIN = 70.1MHz, PGA = 0, Dither "On"
140 120 SFDR (dBc AND dBFS) 100 SFDR (dBc) 80 60 40 20 0 -70 110 105 100
SNR (dBFS)
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
LTC2203: SNR and SFDR vs Sample Rate
110 105 SNR AND SFDR (dBFS) 100 95 90 85 SNR 80 75 0 5 10 15 20 25 30 35 40 45 50 SAMPLE RATE (Msps)
22023 G34
RATED MAX SFDR
SNR SFDR (dBFS)
95 90 85 80 75 2.8
IVDD (mA)
10
UW
-10
22032 G31
LTC2203: 32K Point 2-Tone FFT, fIN = 44.9MHz and 70.1MHz, -15dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 8 4 6 FREQUENCY(MHz) 10 12
22032 G29
LTC2203: SFDR vs Input Level, fIN = 70.1MHz, PGA = 0, Dither "Off"
140 120 100 80 60 40 20 0 -70
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
22023 G30
LTC2203: SFDR (HD2 or HD3) vs Input Frequency
82 81
LTC2203: SNR vs Input Frequency
PGA = 0 80 PGA = 1 79 78 77 76 75 74 0 20 80 60 INPUT FREQUENCY (MHz) 40 100
22023 G32
95 90 PGA = 0 85 80 75
PGA = 1
0
70
73 0 20 60 40 80 100 120 INPUT FREQUENCY (MHz) 140
22023 G33
LTC2203: SNR and SFDR vs Supply Voltage (VDD), fIN = 5MHz
110 105 70 100 SFDR 65 LOWER LIMIT UPPER LIMIT 75
LTC2203: IVDD vs Sample Rate, 5MHz Sine Wave, -1dBFS
60
SNR
55
2.9
3.0
3.4 3.5 SUPPLY VOLTAGE (V)
3.1
3.2
3.3
3.6
50
0
5
15 20 10 SAMPLE RATE (Msps)
25
22023 G36
22023 G35
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LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: Normalized Full Scale vs Temperature, Internal Reference, 5 Units
1.01 6 4 NORMALIZED FULL SCALE OFFSET VOLTAGE (mV) 1.005 2 SFDR (dBc) 40 20 0 TEMPERATURE (C) 80
22023 G38
1
0.995
0.99 -40
-20
0 20 40 TEMPERATURE (C)
LTC2202: Integral Nonlinearity (INL) vs Output Code
2.0 1.5 1.0 INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 CODE
22023 G40
DNL ERROR (LSB)
0 0.2 0.4 0.6 0.8
COUNT
49152
LTC2202: 128K Point FFT, fIN = 5.1MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1 2 3 FREQUENCY (MHz) 4 5
22023 G43
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G44
AMPLITUDE (dBFS)
UW
60 80
22023 G37
LTC2203: Offset Voltage vs Temperature, 5 Units
110 105 100 95 90 85 80 75 70 65 -6 -40 60 -20 60
LTC2203: SFDR vs Input Common Mode Voltage, fIN = 5MHz, -1dBFS, PGA = 0
0 -2 -4
0.5
0.75 1.25 1.50 1.75 1 INPUT COMMON MODE VOLTAGE (V)
2
22023 G39
LTC2202: Differential Nonlinearity (DNL) vs Output Code
1.0 0.8 0.6 0.4 0.2 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 16384 32768 CODE 49152 65536
22023 G41
LTC2202: AC Grounded Input Histogram (256K Samples)
65536
1.0
0 32793
32797
32801 32805 OUTPUT CODE
32809
22023 G42
LTC2202: 128K Point FFT, fIN = 5.1MHz, -10dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 128K Point FFT, fIN = 5.1MHz, -20dBFS, PGA = 0, Internal Dither "Off"
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G45
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LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2203: 128K Point FFT, fIN = 5.1MHz, -20dBFS, PGA = 0, Internal Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1 2 3 FREQUENCY (MHz) 4 5
22023 G46
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G47
AMPLITUDE (dBFS)
LTC2202: SFDR vs Input Level, fIN = 5MHz, PGA = 0, Dither "Off"
120 100 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 80 60 40 20 0 -70 140 120
80 60 40 20 0 -70
AMPLITUDE (dBFS)
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point FFT, fIN = 12.4MHz, -10dBFS, PGA = 0
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
1
2 3 FREQUENCY (MHz)
12
UW
-10
22023 G49
LTC2202: 32K Point 2-Tone FFT, fIN = 5.1MHz and 15.2MHz, -7dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point 2-Tone FFT, fIN = 5.1MHz and 15.2MHz, -15dBFS, PGA = 0
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G48
LTC2202: SFDR vs Input Level, fIN = 5MHz, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point FFT, fIN = 12.4MHz, -1dBFS, PGA = 0
100
0
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G51
22023 G50
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point FFT, fIN = 12.4MHz, -20dBFS, PGA = 0
120 100 80 60 40 20
LTC2202: SFDR vs Input Level, fIN = 12.4MHz, PGA = 0, Dither "Off
4
5
22023 G52
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G53
0 -70
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
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22023 G54
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: 32K Point FFT, fIN = 30.5MHz, -1dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1 2 3 FREQUENCY (MHz) 4 5
22023 G55
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G56
AMPLITUDE (dBFS)
LTC2202: SFDR vs Input Level, fIN = 30.1MHz, PGA = 0, Dither "Off"
140 120 SFDR (dBc AND dBFS) 100 80 60 40 20 0 -70 SFDR (dBc AND dBFS) 140 120
80 60 40 20 0 -70
AMPLITUDE (dBFS)
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
LTC2202: 32K Point FFT, fIN = 70.1MHz, -10dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1 2 3 FREQUENCY (MHz) 4 5
22023 G61
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
UW
-10
22023 G58
LTC2202: 32K Point FFT, fIN = 30.5MHz, -10dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point FFT, fIN = 30.5MHz, -20dBFS, PGA = 1
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G57
LTC2202: SFDR vs Input Level, fIN = 30.1MHz, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
LTC2202: 32K Point FFT, fIN = 70.1MHz, -1dBFS, PGA = 1
100
0
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
0
1
2 3 FREQUENCY (MHz)
4
5
22023 G60
22023 G59
LTC2202: 32K Point FFT, fIN = 70.1MHz, -20dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1 2 3 FREQUENCY (MHz) 4 5
22023 G62
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LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: 32K Point 2-Tone FFT, fIN = 60.2MHz and 70.1MHz, -7dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 FREQUENCY (MHz) 4
22023 G63
SFDR (dBc AND dBFS) 0 2 FREQUENCY (MHz) 4
22023 G64
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2202: SFDR vs Input Level, fIN = 70.1MHz, PGA = 0, Dither "On"
140 120 SFDR (dBc AND dBFS) 100 80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) SFDR(dBc) 110 105 100
SNR (dBFS)
LTC2202: SNR and SFDR vs Sample Rate
110 105 SNR AND SFDR (dBFS) 100 95 90 85 80 75 0 4 8 12 16 20
22023 G69
SFDR SNR SFDR (dBFS)
SNR 80 75 2.8
14
UW
22023 G66
LTC2202: 32K Point 2-Tone FFT, fIN = 60.2MHz and 70.1MHz, -15dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 140 120 100 80 60 40 20
LTC2202: SFDR vs Input Level, fIN = 70.1MHz, PGA = 0, Dither "Off"
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
22023 G65
LTC2202: SFDR (HD2 or HD3) vs Input Frequency
82 81 80 PGA = 1 95 90 85 80 75 0 70 0 20 80 60 INPUT FREQUENCY (MHz) 40 100
22023 G67
LTC2202: SNR vs Input Frequency
79 78 77
PGA = 0
PGA = 1 76 75 74 73 0 20 60 40 80 100 120 INPUT FREQUENCY (MHz) 140
PGA = 0
22023 G68
LTC2202: SNR and SFDR vs Supply Voltage (VDD), fIN = 5MHz
110 105 SFDR 100 95 90 85 LOWER LIMIT UPPER LIMIT
RATED MAX
SNR
2.9
SAMPLE RATE (Msps)
3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V)
3.5
3.6
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22023 G70
LTC2203/LTC2202 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2202: IVDD vs Sample Rate, 5MHz Sine Wave, -1dBFS
50 49 NORMALIZED FULL SCALE 48 47 IVDD (mA) 46 45 44 43 42 41 40 0 2 6 8 4 SAMPLE RATE (Msps) 10
22023 G71
LTC2202: Offset Voltage vs Temperature, 5 Units
6 4 OFFSET VOLTAGE (mV) 2 SFDR (dBc) 0 -2 -4 -6 -40 110 105 100 95 90 85 80 75 70 65 60 -20 40 20 0 TEMPERATURE (C) 60 80
22023 G73
UW
LTC2202: Normalized Full Scale vs Temperature, Internal Reference, 5 Units
1.01
1.005
1
0.995
0.99 -40
-20
0 20 40 TEMPERATURE (C)
60
80
22023 G72
LTC2202: SFDR vs Input Common Mode Voltage, fIN = 5MHz, -1dBFS, PGA = 0
0.5
0.75 1.25 1.50 1.75 1 INPUT COMMON MODE VOLTAGE (V)
2
22023 G74
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LTC2203/LTC2202 PI FU CTIO S
SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD with 1k or less to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.5V (PGA = 0). VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F. Ceramic chip capacitors are recommended. VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pins 5, 8, 9, 11, 15, 48, 49): ADC Power Ground. AIN+ (Pin 6): Positive Differential Analog Input. AIN- (Pin 7): Negative Differential Analog Input. CLK (Pin 10): Clock Input. The hold phase of the sampleand-hold circuit begins on the falling edge. The output data may be latched on the rising edge of CLK. SHDN (Pin 16): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 17): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital Outputs. D15 is the MSB. OGND (Pins 23, 31 and 38): Output Driver Ground. OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1F capacitor. CLKOUT- (Pin 29): Data Valid Output. CLKOUT- will toggle at the sample rate. Latch the data on the falling edge of CLKOUT-. CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. OF (Pin 43): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. OE (Pin 44): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. MODE (Pin 45): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 46): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference. PGA (Pin 47): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.5VP-P. High selects a front-end gain of 1.5, input range of 1.667VP-P. GND (Exposed Pad, Pin 49): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground.
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LTC2203/LTC2202 BLOCK DIAGRA
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND
AIN-
DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER
RANGE SELECT SENSE PGA VCM ADC REFERENCE
BUFFER VOLTAGE REFERENCE OGND CLK SHDN PGA RAND M0DE DITH OE
22032 F01
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VDD ADC CLOCKS OVDD CLKOUT+ CLKOUT- OF LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS D15 D14 D1 D0 * * *
Figure 1. Functional Block Diagram
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = -20Log((V22 + V32 + V42 + ... VN2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when CLK reaches 0.45 of VDD to the instant that the input signal is held by the sample-andhold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER)
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
CONVERTER OPERATION The LTC2203/LTC2202 are CMOS pipelined multistep converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. The phase of operation is determined by the state of the CLK input pin. When CLK is high, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "input S/H" shown in the block diagram. At the instant that CLK transitions from high to low, the voltage on the sample capacitors is held. While CLK is low, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the low phase of CLK. When CLK goes back high, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes low, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer.
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SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2203/ LTC2202 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transitors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.
LTC2203/02 VDD CSAMPLE 9.1pF CPARASITIC 1.4pF AIN+ VDD CSAMPLE 9.1pF CPARASITIC 1.4pF AIN- CLK
22032 F02
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Figure 2. Equivalent Input Circuit
During the sample phase when CLK is high, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When CLK transitions from high to low, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from low to high, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time at the input of the converter. If the change between the last sample and
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19
LTC2203/LTC2202 APPLICATIO S I FOR ATIO
the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input may swing 0.625V for the 2.5V range (PGA = 0) or 0.417V for the 1.667V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2F or greater. Input Drive Impedence As with all high performance, high speed ADCs the dynamic performance of the LTC2203/LTC2202 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the rising edge of CLK the sample and hold circuit will connect the 9.1pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK falls, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FCLK); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recomended to have a source impedence of 100 or less for each input. The source impedence should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. INPUT DRIVE CIRCUITS Figure 3 shows the LTC2203/LTC2202 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows
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a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.
VCM ANALOG INPUT T1 1:1 AIN+ 12pF 12pF AIN- T1 = COILCRAFT WBCI-IT OR MA/COM ETC1-1T. RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE, EXCEPT 2.2F. 12pF
22032 F03
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LTC2203/02
Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 1MHz to 100MHz
Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4 shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V.
VCM 2.2F 0.1F ANALOG INPUT 0.1F T1 1:1 4.7pF 4.7pF AIN+ LTC2203/02
0.1F
AIN- 4.7pF
22032 F04
T1 = MA/COM ETC1-1-13. RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE, EXCEPT 2.2F.
Figure 4. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 50MHz to 250MHz
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
Figure 5 demonstrates the use of an LTC1994 differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp will limit the SFDR at high input frequencies.
2.2 F 499 100pF 523 AIN+ LTC2203/02 VCM
- +
+
100pF AIN- 100pF
CM LT1994 499 53.6 499
-
Figure 5. DC Coupled Input with Differential Amplifier
The 25 resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. Reference Operation Figure 6 shows the LTC2203/LTC2202 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2203/LTC2202 has three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use the external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.5VP-P (PGA = 0). A 1.25V output, VCM, is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2F.
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The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and is not accessible for external use.
LTC2203/02 RANGE SELECT AND GAIN CONTROL SENSE PGA TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE INTERNAL ADC REFERENCE 2.5V BANDGAP REFERENCE VCM 2.2F BUFFER 1.25V
22032 F05 22032 F07
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Figure 6. Reference Circuit
The SENSE pin can be driven 5% around the nominal 2.5V or 1.25V external reference input. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with at least a 1F ceramic capacitor.
VCM 2.2F 2 6 SENSE 2.2F LTC2203/02
1.25V
3.3V 1F
LT1461-2.5 4
22032 F08
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.5VP-P; PGA = 1 selects an input range of 1.667VP-P. The 2.5V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be 2.4dB worse. See the Typical Performance Characteristics section. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (Figure 8).
CLEAN 3.3V SUPPLY FERRITE BEAD 0.1F SINUSOIDAL CLOCK INPUT 0.1F 1k CLK 56 1k NC7SVU04 LTC2203/02
4.7F
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Figure 8. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2203/2202 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.
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In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. It is also helpful to drive the CLK pin with a low-jitter high frequency source which has been divided down to the appropriate sample rate. If the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2203 is 25Msps. The maximum conversion rate for the LTC2202 is 10Msps. For the ADC to operate properly the CLK signal should have a 50% (5%) duty cycle. Each half cycle must have at least 18.9ns for the LTC2203 internal circuitry to have enough settling time for proper operation. For the LTC2202, each half cycle must be at least 40ns. An on-chip clock duty cycle stabilizer may be activated if the input clock does not have a 50% duty cycle. This circuit uses the falling edge of CLK pin to sample the analog input. The rising edge of CLK is ignored and an internal rising edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2203/LTC2202 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2203/LTC2202 is 1Msps.
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output buffer in CMOS Mode. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2203/LTC2202 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs.
LTC2203/02 OVDD VDD VDD 0.5V TO 3.6V 0.1F OVDD DATA FROM LATCH PREDRIVER LOGIC 43 TYPICAL DATA OUTPUT OGND
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Figure 9. Equivalent Circuit for a Digital Output Buffer
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Data Format The LTC2203/LTC2202 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin.
Table 1. MODE Pin Function
MODE 0(GND) 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2's Complement 2's Complement Clock Duty Cycle Stabilizer Off On On Off
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Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow. Output Clock The ADC has a delayed version of the CLK input available as a digital output. Both a noninverted version, CLKOUT+ and an inverted version CLKOUT- are provided. The CLKOUT+/CLKOUT- can be used to synchronize the converter data to the digital system. This is necesary when using a sinusoidal clock. Data can be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT-. CLKOUT+ falls and CLKOUT- rises as the data outputs are updated.
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is "Randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high.
LTC2203/02 CLKOUT CLKOUT
RAND = HIGH, SCRAMBLE ENABLED
RAND
D0
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Figure 10. Functional Equivalent of Digital Output Randomizer
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OF OF D15 D15/D0 D14 D14/D0 D2
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* * *
D2/D0
D1
D1/D0
D0
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.
PC BOARD FPGA CLKOUT
LTC2203/02 D14/D0 D14
Figure 11. Descrambling a Scrambled Digital Output
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OF D15/D0 D15 D2/D0
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* * *
D2
D1/D0 D1
D0
D0
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO
Internal Dither The LTC2203/LTC2202 are 16-bit ADCs with very linear transfer functions; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input's location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 12, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off.
LTC2203/02 AIN+ ANALOG INPUT AIN- S/H AMP 16-BIT PIPELINED ADC CORE DIGITAL SUMMATION OUTPUT DRIVERS CLKOUT+ CLKOUT- OF D15 * * * D0
CLOCK/DUTY CYCLE CONTROL
PRECISION DAC
MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR
CLK
DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF
Figure 12. Functional Equivalent Block Diagram of Internal Dither Circuit
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Grounding and Bypassing The LTC2203/LTC2202 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2203/LTC2202 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2203/LTC2202 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2203/LTC2202 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible.
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Evaluation Circuit Schematic of the LTC2203/LTC2202
VDD OVP 3 5 2 JP3 OPEN PGA VDD R6 OPEN 1 OVP VDD 2 VCC GND 3 11 B7 B6 B5 B4 B3 B2 B1 B0 OE GND T/R 1 10 R5 33 1 3 5 RN1A, 33 RN1B, 33 RN1C, 33 OVP 20 VCC RN1D, 33 RN2A, 33 RN2B, 33 RN2C, 33 RN2D, 33 A7 11 12 13 C28 0.1F C15 0.1F C16 0.1F C17 0.1F 14 15 16 17 18 19 VDD R20 10k B7 B6 B5 B4 B3 B2 B1 B0 OE T/R GND 1 10 A6 U3 74VCX245BQX A5 A4 A3 A2 A1 A0 9 8 7 6 5 4 3 2 RN3A, 33 RN3B, 33 RN3C, 33 RN3D, 33 RN4A, 33 RN4B, 33 RN4C, 33 RN4D, 33 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 U2 74VCX245BQX A6 8 A7 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 17 18 OVDD D11 D10 D9 D8 U1* EXPOSED PAD OGND CLKOUT + CLKOUT - D7 D6 D5 OVDD VDD VDD GND SHDN DITH D0 D1 D2 D3 D4 OGND OVDD GND 25 26 27 28 29 30 31 32 33 34 35 19 36 OE OF D15 D14 D13 GND PGA D12 RAND MODE OGND OVDD 9 R8 51 C2 2.2F R10 5.1 GND 3 2 VDD 20 3 R7 1K OVP GND C1 0.1F 1 JP4 RAND 1 2 4 U4 NC7SV86P5X
JP2 SENSE R1 10K R2 10K R3 1K R4 OPEN 2
DCIN+
R31 O
R26 10
R27 10
R32 0 C3 8.2pF C5 8.2pF 1 SENSE VCM VDD VDD GND AIN + AIN - GND GND/ENC + GND/ENC - GND VDD 2 C7 8.2pF 3 5.1 5 6 7 8 R33 * 9 10 4 VDD 12 3 OSC1 OPT. FO 13 14 15 16 17 18 19 20 21 22 23 24 GND 2 49 R30 OPEN 11 R28 33 C8 2.2F 4 ENCODE INPUT J3 VDD
R9 OPEN
APPLICATIO S I FOR ATIO U
2 4 6 J1 3201S-40G1 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 OGND
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ANALOG INPUT
OPEN
C4
5
T1
1
R11 OPEN
J2
R24 OPEN
C6
4
3
ETC1-1T
OPEN
R12 OPEN
C9 0.1F
R13 OPEN
VDD
R29 1k
1
EN
* VERSION TABLE MSPS 3 3 105 80 65 40 1 1 OVP VDD E1 VDD + 3.3V R22 105K 1 2 C20 10F 6.3V GND E4 3 R23 100K C21 0.01F 4 25 10 VDD VDD GND 22 GND JP6 DITH JP6 DITH
R21 10k
ASSEMBLY TYPE 16 16 16 16 16 16
U1
R33
INPUT FREQUENCY
BITS
DC919A-A
LTC2207CUK
0.01F
DC < AIN < 70MHz
5 C18 0.1F C19 0.1F 4 U5 NC7SV86P5X 3
DC919A-B
LTC2206CUK
0.01F
DC < AIN < 70MHz
1 2 C14 0.1F 1 2 3 U7 LT1763 OUT ADJ GND BYP IN GND GND SHDN VDD 8 7 6 5 C22 1.0F R25 1 C25 0.1F C26 0.1F OVP 4
DC919A-C
LTC2205CUK
0.01F
DC < AIN < 70MHz
R17 10K U6 24LC025 VCC A0 A1 A2 A3 WP SCL SDA 8 7 6 5
R18 10K
R19 10K
DC919A-D
LTC2204CUK
0.01F
DC < AIN < 70MHz
C13 0.1F
DC919A-E
LTC2203CUK
0
DC < AIN < 70MHz
DC919A-F
LTC2202CUK
0
DC < AIN < 70MHz
+ C27
100F 6.3V OPT E3
C23 4.7F
U LTC2203/LTC2202
2
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO U
Silkscreen Top Silkscreen Topside
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO U
Inner Layer 2 Inner Layer 3
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LTC2203/LTC2202 APPLICATIO S I FOR ATIO U
Silkscreen Bottom Side Silkscreen Bottom
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LTC2203/LTC2202 PACKAGE DESCRIPTIO U
UK Package 48-Lead Plastic QFN (7mm x 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 0.05 5.50 REF 6.10 0.05 7.50 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP R = 0.10 TYP 47 48 0.40 0.10 1 2 PIN 1 CHAMFER C = 0.35 5.15 0.10 5.50 REF (4-SIDES) 5.15 0.10 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(UK48) QFN 0406 REV C
5.15 0.05
5.15 0.05
PIN 1 TOP MARK (SEE NOTE 6)
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC2203/LTC2202 RELATED PARTS
PART NUMBER LTC1748 LTC1750 LT1993-2 LT1994 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2220-1 LTC2224 LTC2242-12 LTC2255 LTC2284 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps ADC 14-Bit, 80Msps Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 40Msps, 3.3V ADC 16-Bit, 65Msps, 3.3V ADC 16-Bit, 80Msps, 3.3V ADC 16-Bit, 105Msps, 3.3V ADC 16-Bit, 130Msps, 3,3V ADC, LVDS Outputs 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 480mW, 79.1dB SNR, 100dB SFDR, 48-Pin QFN 610mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50 Single Ended RF and LO Ports
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0507 REV B * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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